1. Field of the Invention
This disclosure relates to a data path circuit and method and, more particularly, to a circuit for bidirectional data transfer for increasing a bandwidth of information exchanged between a plurality of entities.
2. Description of the Related Art
Metal interconnect adds significantly to the cost of VLSI circuits. Wiring resources are constrained either by the cost of additional wiring levels or by the improvements in process and lithography required to increase wiring density. One way to better utilize the scarce wiring resource is to share bus wires between macros. For chip to chip communications, a prior art approach described in U.S. Pat. No. 5,604,450 by Borkar et al. achieves bidirectional signaling by employing a ternary encoding scheme. While this scheme may achieve higher throughput at the board level, it comes at great expense to be deployed for chip (unit/macro) level wire interconnect. A more satisfactory solution is desirable which neither degrades signal noise margin nor consumes DC power.
A shared bus, or what is called a tristate bus, enables more than one sending entity to control the state of the bus. Unfortunately, in most tristate bus schemes, a signal wire can only transfer one bit of information each cycle. Each sending entity must time share a bus with the other sending entities using that same bus, otherwise, logic conflicts would arise between a driver trying to pull a net low to a "0" and another trying to pull the same net high to a "1". Hence in all the above mentioned schemes, only one driver can be active during any given cycle; the other drivers attached to the net are put into a high impedance state. While a shared bus scheme may save wiring resources, it does not increase the potential throughput, or bandwidth, of the bus. To achieve improved bandwidth, the bus must be time shared over a single cycle.
Therefore, a need exists for a circuit, which could be inserted near the center of a bus for exchanging data on bus wires connecting two or more entities in such a way that two waves of data, moving in opposite directions, may simultaneously exist on the bus without colliding data.